Résumé/CV – Gabriel Feng

Education

Ph.D., Electrical Engineering and Computer Science (EECS) · Aug 2026 – present

B.S. Physics and B.S. Electrical Engineering, AI/ML minor · May 2026

GPA 3.97 / 4.0
Honors: College of Science Dean’s Scholar, President’s Undergraduate Research Award, SCALE DoD HIAP Scholar
Coursework: semiconductor devices, IC fabrication, advanced packaging, analog IC design, solid-state physics, quantum mechanics, quantum information and computing, statistical mechanics, machine learning

Graduate Researcher · PI: Prof. Tomás Palacios · Cambridge, MA · Aug 2026 – present

Developing GaN HEMTs with 100 nm L_SD and graded Al_xGa_1−xN devices for high-voltage operation
Characterizing graded AlGaN etch rates; 2D device modeling in TCAD and exploring ML-enhanced quantum transport
Calibrating 2D device fabrication with e-beam lithography dose tests and transfer length method (TLM) contacts

Research Intern · PI: Prof. Jud Ready · Atlanta, GA · May 2023 – May 2026

Integrated a 28-step process flow for carbon nanotube field emission array (CNTFEA) chips for Hall-effect thrusters
Iteratively refined process parameters including etch chemistry, deposition time, doping conditions and metrology recipes
Validated CNT field emission with a custom LabVIEW-controlled high-voltage system, confirming tunneling behavior
Awarded the President’s Undergraduate Research Award to investigate alternative gate thin films for triode-type CNTFEAs
Characterized sub-10 µm features with SEM, EDS, reflectometry and profilometry to diagnose fabrication deviations

Undergraduate Researcher · PIs: Prof. Muhannad Bakir, Prof. Thomas Gaylord · Atlanta, GA · Oct 2024 – May 2026

Fabricated micro-packages using TSHs and angled surface-coupling waveguide designs for optical fiber integration
Patterned, developed and cured positive self-alignment structures (PSAS) for sub-micron alignment accuracy
Demonstrated optical coupling with <2 dB loss in passive grating-coupler waveguides through tilted chiplet assembly

Undergraduate Researcher · PIs: Prof. Claire Berger, Prof. Walter de Heer · Atlanta, GA · Apr 2023 – Dec 2024

Revived an ellipsometer and created recipes for BN layers (2–20 nm), verified with AFM
Performed NMF-based deconvolution of Raman spectra for graphene G and 2D peaks
Designed, assembled and calibrated a low-temperature PVD furnace for selenium with HV chamber components
Built a vacuum four-point Van der Pauw probe station to measure graphene under controlled conditions
Characterized carrier density and mobility of graphene through Hall-effect and Van der Pauw measurements

Semiconductor R&D Intern · Supervisor: Dr. Will Green · Albany, NY · May – Aug 2026

Designed co-packaged optics (CPO) devices; collaborated on process integration with IBM Research Zurich and Bromont
Designed an adiabatic mono-taper for a 44% footprint reduction in IBM CPO, taped out in 2027-generation modules
Developed 3D photonic-integration EDA software using A* and negotiated-congestion algorithms with photonic-aware heuristics
Migrated Sentaurus TCAD (SWB) CFET decks to SPython and built an internal agent to automate the migration

Metrology Applications Intern · Supervisor: Dr. Chaoyue Becker · Austin, TX · May – Aug 2025

Identified and analyzed critical defects in 14 nm FinFET technology using dark-field inspection and SEM review
Developed a cloud-based scoring application to evaluate dark-field scan recipes ahead of pre-VOC readiness
Integrated a CNN-based signature detection algorithm to validate scan accuracy and flag recipe and device weaknesses
Ran optics-selector studies across dielectric and metal films, improving defect detection by up to 117%
Documented polarization for film- and topography-dependent laser scattering, for process-level tuning at the 4 nm node
Investigated defects of interest with the process and yield teams to perform FMEA

Semiconductor Process Engineering Intern · Supervisor: Dr. Junsic Hong · Linthicum, MD · May – Aug 2024

Maintained (PE)ALD and (PE)CVD films for pHEMT, SLCFET and HBT devices, holding process specs with SPC
Studied the stress of ALD films and found the plasma/thermal Al₂O₃ ratio for zero-stress films
Reduced the contact angle of PECVD Si₃N₄ films by ~80%, optimizing surface energy for photoresist primer
Created an in-situ plasma surface-termination recipe that tunes the contact angle between 5° and 60° without degrading the film
Wrote a Python script that predicts precursor cycle limits before an ALD tool fault, recovering a production wafer lot

IC Fabrication (ECE 4452) · Atlanta, GA · Aug – Dec 2024

Modeled junction depth and dopant concentration to refine the process flow
Fabricated PMOS/NMOS transistors, Van der Pauw structures, logic gates, capacitors and ring oscillators
Tested the devices: I–V curves of 2 µm transistors, oscillator clock cycles and resistances, correlated with process non-idealities

Electronics Lead · Atlanta, GA · Aug 2022 – May 2023

Led the design of an experimental apparatus for Georgia Tech’s Low Turbulence Wind Tunnel
Built a load-cell interface to measure drag across parachute reefing states
Designed and programmed a reefing crank that cut descent time by 30%

Georgia Institute of Technology · Atlanta, GA · Jan 2023 – Dec 2024

Lectured before labs and demonstrated equipment and software
Graded lab reports and worked with professors on lab material for classes of ~200 students
Tutored math and physics one-on-one through the 3000 level

S. Yu, G. Feng, T. K. Gaylord and M. S. Bakir, “Self-Aligned Fiber Coupling using Tilted-Si Chiplets for Photonic Integration,” IEEE Photonics Technology Letters, 2026 (under revision).
G. Feng and J. Ready, “Alternative Gate Thin Films for Triode-Type CNTFEAs,” poster, TMS Annual Meeting & Exhibition, Las Vegas, NV, March 2025.

Equipment: 500+ hours in ISO 5 cleanrooms; deposition (ALD, PEALD, CVD, PECVD, PVD), oxidation and doping furnaces, spinners, masked and maskless aligners, RIE, wet etch, e-beam and UV lithography, dicing
Characterization: reflectometry, profilometry, probing, SEM, AFM, Raman, ellipsometry, oscilloscopes, dark-field inspection
Vendors: Applied Materials, TEL, Plasma-Therm, Canon, Cambridge, Oxford, Tystar, Karl Suss, KLA-Tencor, Horiba
Software: Python, Java, VHDL, MATLAB, Spotfire, SPC, JMP, SQL, CAD, TCAD, TensorFlow, COMSOL, Linux, LaTeX
Fabricated: CNTFEAs, FISCT-T, MOSFETs, ring oscillators, capacitors, resistors; FinFET (metrology), SLCFET (ALD/PECVD)